Many-core and multi-core devices provide a way to increase performance of a device without incurring the cost of increasing clock speeds. Many-core devices may include dedicated ASIC blocks for hardware specific functions that are often referred to as hardware accelerators. Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs)), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) generally include programmable logic blocks which may be configured to implement various operations. Some PLDs also include configurable embedded hardware to support additional operations. However, conventional approaches to configuring such embedded hardware are often cumbersome and unwieldy.
One limitation of existing many-core and multi-core systems is that the topology and node configuration of the system is fixed. In these systems, tasks are run separately, and physical copies of data are passed between computing nodes and applications, which is inefficient. Accordingly, there is a need for an improved approach to configuring hardware resources of a PLD.